Steve Furber University of Manchester THE INCREASING COMPLEXITY OF SYSTEM - ON - A - CHIP DESIGNS EXPOSES THE LIMITS IMPOSED
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چکیده
A globally shared bus increasingly cannot meet the demands of system-on-a-chip (SOC) interconnects because the high wire loads and resistance levels result in slow signal propagation. A popular alternative, using unidirectional point-to-point connections, and multiplexers, requires even more chip space and still suffers from many of the same problems (for example, difficulties in timing validation and connecting devices running from unrelated clocks). Furthermore, to continue increasing the number and variety of macrocells embedded on a single chip will require interconnects with greater flexibility than today’s synchronous, core-specific system buses. The adoption of on-chip networks as the solution to growing SOC interconnect demands, presented by both current and projected integration levels, raises the question of which clocking strategy to use. A higher clock frequency produces better performance, but by definition, the global interconnect spans the entire chip—exactly the situation that leads to clock skew problems. Clock management of such a network is problematic at best. Using self-timed techniques for the network on a chip eliminates these problems. This leaves only the issue of interfacing synchronous and self-timed circuits, which is a well understood discipline for which standard solutions exist.
منابع مشابه
Task Graph Mapping of General Purpose Applications on a Neuromorphic Platform
Indar Sugiarto∗, Pedro Campos†, Nizar Dahir‡, Gianluca Tempesti§ and Steve Furber¶ ∗¶School of Computer Science, University of Manchester, United Kingdom †§Department of Electronics, University of York, United Kingdom ‡IT Research and Development Center, University of Kufa, Iraq ∗¶{indar.sugiarto, steve.furber}@manchester.ac.uk, †§{pedro.campos, gianluca.tempesti}@york.ac.uk ‡nizar.dahir@uokufa...
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تاریخ انتشار 2001